The increase in computing power and the development of low-power computing, quantum computing, and the Internet of Things require lossless and reliable approaches to information processing. Based on previous results, this work aims to develop a new fault-tolerant reversible encryption device with an optimal number of components, delay time and auxiliary ports. Empirical analysis of known reversible reconfigurable encryptors and alternative reversible basis was used. The work results presented two new reversible encryptors based on the reconfigured extended basis of Fredkin gates. Comparisons with known reversible encryptors showed at least a 39% improvement in quantum cost and a reduction in circuit depth of more than 52%. Notably, the quantum cost was reduced from 79 to 19 (to 48 in case of variant with preservation of parity) due to the improvement of the circuit design. The circuit depth was reduced from 9 to 5 (to 6 in case of circuit with preservation of parity). One of the synthesised encryptors preserves parity, improving the fault tolerance of the device. The simulation of the encoder models was carried out in the Active-HDL environment, and the quantum parameters of the devices were determined using the IBM Quantum Lab. The outcomes of the study produced promising reconfigurable reversible circuits for data processing.