Post-quantum cryptography will be the future standard of cryptography resistant to quantum and classical computers. The migration to quantum-safe products is not without a significant impact on hardware designs and capacities. In addition to mathematical security, the security of implementations regarding physical attacks: side-channel and faults, has to be taken into account. In this paper, we present a performances analysis of a full masked implementation in software of DILITHIUM. We provide a quantitative analysis of the bottlenecks introduced by the countermeasures in different configurations: from full software to implementation using assembly code for Keccak core, and, AES in hardware for seed extension. This work contributes to define the specifications of future hardware capabilities of components providing quantum-safe security services.