The approximate multipliers allow saving power and area by deploying many other contemporary, error flexible, compute intensive application. In this manuscript, first discussed an original minimally biased approximate integer multiplier design method that can be configured with an error. The proposed MBM architecture by combining by an approximated ‘Log’ biased numeral multiplier of a specific error reduction mechanism. After that analysed a place of original estimated floating point (FP) multiplier. These are showing to facilitate these FP multipliers is on the Pareto obverse on the region designs space against power and error. Here used the 45-nm criterion cell library to synthesis the designs. When compared to the precise version we designed MBM integer offers 84% power reduction and 78% area reduction. The proposed estimated FP multiplier offers improved error effectiveness than the precise scaling. The discussed FP multiplier offers 57% power and 25% area improvements. It isa smaller amount of 4% error bias, 8% mean error and 28% of peak error.