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RISC-V Based Safety System-on-Chip with Hardware Comparator
Eike Hahn, Dominik Kalinowski, Waldemar Mueller, Mohamed Abdelawwad, Josef Boercsoek
362 - 368
10.3233/FAIA210423
Research Article
Frontiers in Artificial Intelligence and Applications
Volume 345: Proceedings of CECNet 2021
Abstract

In this paper, a Safety System-on-Chip based on the open-source RISC-V processor SweRV EH1 from Western Digital is presented. A hardware comparator concept is followed. The SSoC is implemented on a Xilinx FPGA system and extended with standard peripherals from the Xilinx IP library and from Cobham Gaisler, so that the overall system has an Ethernet interface in addition to GPIO and UART. The goal is to create a complete redundancy approach with a hardware fault tolerance of nearly 1 from input to output based on the freely available RISC-V instruction set and prove its feasibility.

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