A fast-settling dual-path fractional-N phase-locked loop (PLL) is presented in this paper, which is applied for frequent current charging and discharging. Compared with the conventional phase-locked loop, this one is significantly able to reduce the settling time with hybrid approaches. By employing direct presetting frequency, based on frequency-locked loop (FLL), the process locking is accelerated. To achieve low phase noise, 20-bits delta-sigma modulator is employed in PLL. Dynamic bandwidth is beneficial for both of them and results a smooth transition. Besides, the dual-path fractional-N PLL compensates the nonlinearity from the charge pump (CP), and provides a wider tuning range. Using the 0.6 V supply voltage for 65 nm CMOS, a 900 MHz fractional-N PLL with mixed techniques exhibits less than 2.5 µs transient settling time according the simulation results.