As a guest user you are not logged in or recognized by your IP address. You have
access to the Front Matter, Abstracts, Author Index, Subject Index and the full
text of Open Access publications.
In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 μs and the ripple voltage < −9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.
This website uses cookies
We use cookies to provide you with the best possible experience. They also allow us to analyze user behavior in order to constantly improve the website for you. Info about the privacy policy of IOS Press.
This website uses cookies
We use cookies to provide you with the best possible experience. They also allow us to analyze user behavior in order to constantly improve the website for you. Info about the privacy policy of IOS Press.