This paper proposes a functional verification method for multi-module system field programmable gate array (FPGA) chips. According to the FPGA integrated netlist information, multiple modules to be tested as well as the connection relationship between modules to be tested and the system are all extracted accurately to get a brand-new netlist of modules to be tested. Then the verification excitation is inputted from the outside to verify the extracted netlist, which reduces the compilation time of the large-scale FPGA chip, as well as reduces the configuration time of the chip function verification, accelerates the speed of the simulation, and improves the simulation and verification efficiency. This method has been successfully applied to the FPGA chip circuit function verification engineering practice.