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Digital to Analogue Converters (DACs) connect the digital and analogue world and have thus become important elements in electronic systems. Efficient implementation, high speed and high resolution require the DAC design architecture of choice to be the binary weighted. Therefore, the paper introduces a model to speed up the design and reflect accurately on the behavior of the system prior to component level development and implementation. Furthermore, some of the aspects of designing with binary weighted DAC architecture data devices are considered. The study also covers behavioral modelling of the binary weighted DAC device from an ideal function to reality. The DAC model in this paper yields static characteristics as follows: Gain error of 1 LSB; K of 1.6; Offset voltage of 97 uV; Integral Non-Linearity (INL) error of -3.94E-02 LSB minimum and 5.00E-01 LSB maximum; Differential Non-Linearity error of -3.92E-02 LSB minimum and 2.06E-01 LSB maximum; Step height of 9.61E-01 LSB minimum and 1.21E00 LSB maximum. The DAC model yields fair and practical results as the INL errors are less than or equal to 0.5 LSB; the DNL errors are less than or equal to 2.06E-01 LSB. Additionally, the above errors show that the model yields a design with monotonic behaviour. Moreover, the DAC SFDR analysis shows that there are little variations in the SFDR values across the Nyquist band for the model. However, when frequency goes beyond 100 MHz, there is a degradation in the SFDR values.
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