While the very far future well beyond exaflops computing may encompass such paradigm shifts as quantum computing or neuromorphic computing, a critical window of change exists within the domain of semiconductor digital logic technology but beyond conventional practices of architecture, system software, and programming. As key parameters such as Dennard scaling, nano-scale component densities, clock rates, pin I/O, and voltage represent asymptotic operational regimes, one major area of untapped opportunity is computer architecture which has been severely limited by conventional practices of organization and control semantics. Mainstream computer architecture in HPC has been inhibited in innovation by the original von Neumann architecture of seven decades ago. Although notably diverse in form of parallelism exploited, six major epochs of computer architecture through to the present are all von Neumann derivatives. At their core is the use of single instruction issue and the prioritization of Floating Point ALU (FPU) utilization. However, in the modern age, FPUs consume only a small part of die real estate while the plethora of mechanisms to achieve maximum floating point efficiency take up the majority of the chip. The von Neumann bottleneck, the separation of memory and processor, is also retained. A revolution in computer architecture design is possible by undoing the damage of the von Neumann heritage and emphasizing the key challenges of data movement latency and bandwidth which are the true precious resources along with operation/instruction issue control. This paper discusses key tradeoffs that should drive computer architecture in what might be called the “Neo-Digital Age”.
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