In recent years, hardware obfuscation is one of the prominent anti-tamper solutions that are highly used against various hardware security threats such as piracy, cloning, reverse engineering, chip overbuilding, and hardware Trojans. Logic obfuscation is implemented either in the design description (for soft/firm/hard codes) or structure (for the chip) of electronic hardware to intentionally conceal its functionality. Most of the obfuscation schemes enable the circuit operation in two distinct modes such as obfuscated and normal modes. The mode control, mostly implemented by finite state machine, is performed by the application of a specific sequence of input vectors on initialization, called an ‘initialization key.’ Without the initialization key, it is difficult to comprehend the intended functional behavior of the circuit; hence, circuit tampering or malicious insertion will have a high probability of either becoming functionally benign or easily detectable by conventional logic testing. However, most of the existing obfuscation techniques have used similar obfuscation cell structures throughout the design which in turn leaves a hint to the adversary about circuit obfuscation during reverse engineering. In this paper, we aimed to mitigate this limitation by applying design obfuscation using different obfuscation cells. We performed the hardware obfuscation mechanism for field programmable gate array devices using standard ISCAS'89 benchmark circuits in Actel's ProAsic3 device by Libero SoC v10.1 (free version). We measured the performance overhead using the design parameters such as area, delay, and power.
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