As the Bias Temperature Instability (BTI) effect increase the threshold voltage of transistors and decrease transistors speed, it become a major problem for circuit reliability. Retention registers are used in the power gating architecture. These registers can keep the current states in the always-on blocks. However, they suffer from the BTI effect since the always-on block never is turned off.
This paper proposes 2-bit and 3-bit parallel multi-bit retention registers and investigates the BTI effect on multi-bit retention registers. This paper also uses the selective transistor sizing technique to reduce the degradation. The proposed the multi-bit retention register architecture and design characteristics can reduce the significant area overhead. The experimental results show that compared with the original Dual Control Balloon Register (DCBR), the 2-bit and 3-bit retention registers can reduce area overhead by 27.1% and 34.7%, respectively.
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