Fast Fourier Transform (FFT) plays an important role in Orthogonal Frequency-Division Multiplexing (OFDM) system. This work propose a 4-path Multipath Delay Commutator (MDC) which can increase throughput of FFT processor and propose a method of reducing Twiddle Factor (T. F.) computational circuit area by using trigonometric complementary theorem. The twiddle factor computational circuits can be reached by a right shift circuits, which reduced the design complexity. But different protocols use different FFT-Point. Partial Dynamic Reconfiguration (PDR) capable of switching time-independent circuits, which increase the flexibility of system design. This FFT processor used 64-Point FFT as a static area circuit, and configured other FFT Points as Reconfigurable Modules (RMs). System can configure 64 to 512-Point under different environment. And using PDR also reduced the occupied hardware resources. From experimental results shown that the proposed design can increase the throughput of FFT processor, and maximum reduce 76.6% number of slices and 58.4% number of flip-flops utilization.
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