In this work, dynamic characteristic of a new amorphous silicon gate (ASG) driver circuit is optimized by using multi-objective evolutionary algorithm (MOEA) and hydrogenated amorphous silicon (a-Si:H) TFT circuit simulator on the unified optimization framework (UOF). The ASG driver circuit consisting of 14 a-Si:H TFTs is optimized for the given specifications of the fall time < 3 μs and the ripple voltage < −9 V with simultaneously minimizing the total layout area. More than 50% reductions on the falling time of the ASG driver circuit have been achieved by using the proposed optimization methodology together with a novel 3-level clock driving technique.
IOS Press, Inc.
6751 Tepper Drive
Clifton, VA 20124
Tel.: +1 703 830 6300
Fax: +1 703 830 2300 email@example.com
(Corporate matters and books only) IOS Press c/o Accucoms US, Inc.
For North America Sales and Customer Service
West Point Commons
Lansdale PA 19446
Tel.: +1 866 855 8967
Fax: +1 215 660 5042 firstname.lastname@example.org