With each CMOS technology generation, leakage energy has been increasing at an exponential rate. Since modern processors employ large last level caches (LLCs), their leakage energy consumption has become an important concern in modern chip design. To address this issue, several techniques have been proposed. However, most of these techniques require offline profiling and hence, cannot be used in real-life systems which run trillions of instructions of arbitrary applications. In this paper, we propose Palette, a technique for saving cache leakage energy using cache coloring. Palette uses a small hardware component called reconfigurable cache emulator, to estimate performance and energy consumption of multiple cache configurations and then selects the configuration with least energy consumption. Simulations performed with SPEC2006 benchmarks show the superiority of Palette over existing cache energy saving technique. With a 2MB baseline cache, the average saving in memory sub-system energy and EDP (energy delay product) are 31.7% and 29.5%, respectively.
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